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| ADVANCE INFORMATION CYWB0224ABS/CYWB0224ABM TM TM West Bridge Astoria Features Pseudo CRAM interface (Antioch Interface) Pseudo NAND Flash interface SPI (slave mode) interface DMA slave support N-XpressTM NAND Controller Technology Interleave up to 16 NANDs with 8 Chip Enables (CE#) for x8 or x16 SLC (CYWB0224ABS) or MLC (CYWB0224ABM) NAND flash devices. 4-bit Error Correction Coding Bad Block Management Static Wear Leveling Ultra low power, 1.8V core operation Low Power Modes Small footprint, 6x6mm VFBGA Supports I2C boot and Processor Boot Selectable Clock Input Frequencies Multimedia Device Support Up to 2 SD/SDIO/MMC/MMC+/CE-ATA devices SLIMTM Architecture, allowing simultaneous and independent data paths between the processor and USB, and between the USB and Mass Storage. Fully backward compatible (including pin to pin) to Antioch (CYWB0124AB) High speed USB at 480 Mbps 19.2 MHz, 24 MHz, 26 MHz, and 48 MHz Applications Cellular Phones Portable Media Players Personal Digital Assistants Portable Navigation Devices Digital Cameras POS Terminals Portable Video Recorders USB 2.0 compliant Integrated USB 2.0 transceiver, smart Serial Interface Engine 16 programmable endpoints Flexible Processor Interface, which supports: Multiplexing and nonMultiplexing Address and Data interface SRAM Interface Logic Block Diagram West BridgeTM AstoriaTM Control Registers Flexible Processor Interface uC Access Control P High-Speed USB 2.0 XCVR U SLIMTM SD/SDIO/ MMC+/ CEATA Block Cypress N-XpressTM Engine Configurable Storage Interface S Cypress Semiconductor Corporation Document #: 001-11710 Rev. *A * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised December 7, 2007 [+] Feedback ADVANCE INFORMATION CYWB0224ABS/CYWB0224ABM Functional Overview The SLIMTM architecture The Simultaneous Link to Independent Multimedia (SLIM) architecture allows three different interfaces (P-port, S-port and U-port) to connect to each other independently. With this architecture, a device using Astoria is connected to a PC through a USB, without disturbing any of the functions of the device. The device can still access Mass Storage when the PC is synchronizing with the main processor. The SLIM architecture enables new usage models, in which a PC accesses a Mass Storage device independent of the main processor, or enumerates access to both the Mass Storage and the main processor at the same time. In a handset using SLIM architecture, the user can do the following: cation with the processor, which may have other devices connected on a shared memory bus. Asynchronous accesses can reach a bandwidth of up to 66.7 MBps. Synchronous accesses are performed at 33 MHz across 16 bits for up to 66.7 MBps bandwidth. The memory address is decoded to access any of the multiple endpoint buffers inside Astoria. These endpoints serve as buffers for data between each pair of ports, for example, between the processor port and the USB port. The processor writes and reads into these buffers through the memory interface. Access to these buffers is controlled by using a DMA protocol or using an interrupt to the main processor. These two modes are configured by the external processor. As a DMA slave, Astoria generates a DMA request signal to notify the main processor that a specific buffer is ready to be read from or written to. The external processor monitors this signal and polls Astoria for the specific buffers ready for a read or write operation. It then performs the appropriate read or write operations on the buffer through the processor interface. As a result, the external processor only deals with the buffers to access a multitude of storage devices connected to Astoria. In the Interrupt mode, Astoria communicates important buffer status changes to the external processor using an interrupt signal. The external processor then polls Astoria for the specific buffers ready for read or write, and it performs the appropriate read or write operations through the processor interface. Use the phone as a thumb drive. Download media files to the phone with all the functionalities still available on the phone. Use the same phone as a modem to connect the PC to the internet. 8051 Microprocessor The 8051 microprocessor embedded in Astoria does basic transaction management for all transactions between the P-Port, S-Port, and the U-Port. The 8051 does not reside in the data path; it manages the path. The data path is optimized for performance. The 8051 executes firmware that supports NAND, SD, SDIO, MMC+, and CE-ATA devices at the S-Port. For the NAND device, the 8051 firmware follows the Smart Media algorithm to support the following: USB Interface (U-Port) In accordance with the USB 2.0 specification, Astoria can operate in Full-Speed USB mode in addition to High-Speed USB. The USB interface consists of the USB transceiver. The USB interface can access and be accessed by both the P-Port and the S-Port. The Astoria USB interface supports programmable CONTROL/BULK/INTERRUPT/ISOCHRONOUS endpoints. Physical to Logical Management ECC Correction support Wear Leveling NAND Flash bad blocks handling Mass Storage Support (S-Port) The S-Port may be configured in three different modes, which simultaneously support the following: Configuration and Status Registers The West Bridge Astoria device includes configuration and status registers that are accessible as memory-mapped registers through the processor interface. The configuration registers allow the system to specify some behaviors of Astoria. For example, it can mask certain status registers from raising an interrupt. The status registers convey the status of Astoria, such as the addresses of buffers for read operations. An SD/SDIO/MMC+/CE-ATA port and a x8 NAND port Two SD/SDIO/MMC+/CE-ATA ports Up to eight Chip Enable (CE#) for x8 or x16 NAND flash access port These configurations are controlled by the 8051 firmware. The 16-bit NAND interface is used only when there is no other Mass Storage device connected to the S-Port. N-Xpress NAND Controller (S-Port) Astoria, as part of its Mass Storage management functions, can fully manage the SLC and MLC NAND flash devices. The embedded 8051 manages the actual reading and writing of the NAND, along with its required protocols. It performs standard NAND management functions, such as ECC and wear leveling. The Astoria supports single bit ECC for the SLC and 4-bit ECC for MLC NAND flash. SLC NAND flash devices are supported by CYWB0244ABS. CYWB0244ABM supports both SLC and MLC NAND flash devices. Processor Interface (P-Port) Communication with the external processor is realized through a dedicated processor interface. This interface is configured to support different interface standards. This interface supports multiplexing and nonmultiplexing address or data bus in both synchronous and asynchronous pseudo CRAM-mapped, and nonmultiplexing address or data asynchronous SRAM-mapped memory accesses. The interface may be configured to pseudo NAND interface to support the processor's NAND interface. In addition, this interface may be configured to support the slave SPI interface. This ensures straightforward electrical communiDocument #: 001-11710 Rev. *A Page 2 of 6 [+] Feedback ADVANCE INFORMATION CYWB0224ABS/CYWB0224ABM SD/SDIO/MMC+/CE-ATA Port (S-Port) When Astoria is configured through firmware to support SD/SDIO/MMC+/CE-ATA, this interface supports the following: West Bridge Astoria provides support for 1-bit and 4-bit SD and SDIO cards; 1-bit, 4-bit and 8-bit MMC; MMC+ cards, and CE-ATA drive. For the SD, SDIO, MMC/MMC Plus, and CE-ATA, this block supports one card for one physical bus interface. Astoria supports SD commands including the multisector program command, which is handled by API. The Multimedia Card System Specification, MMCA Technical Committee, Version 4.1. SD Memory Card Specification - Part 1, Physical Layer Specification, SD Group, Version 1.10, October 15, 2004. SD Memory Card Specification - Part 1, Physical Layer Specification, SD Group, Version 2.0, May 9, 2006. SD Specifications - Part E1 SDIO specification, Version 1.10, August 18, 2004. CE-ATA Specification - CE-ATA Digital Protocol, CE-ATA Committee, Version 1.1, September, 2005 Table 1. Astoria Pin Assignments Pin Name Non-multiplexing CLK CE# A0 A1 A[3:2] A4 A5 Multiplexing CLK CE# Ext pull up Ext pull up set A[3:2] = 01 Ext pull up SCL SDA Ext pull up AD[0] AD[1] AD[15:2] ADV# OE# WE# INT# DRQ# DACK# OE# WE# INT# DRQ# DACK# CE# A0 A1 A[3:2] A4 A5 A6 A7 DQ[0] DQ[1] DQ[15:2] SRAM PNAND Ext pull up CS# CLE# RB# set A[3:2] = 00 WP# SCL SDA set A7 to 0 - LBD set A7 to 1 - SBD IO[0] IO[1] IO[15:2] ALE# RE# WE# INT# DRQ# DACK# SCK SS# Ext pull up Ext pull up set A[3:2] = 10 Ext pull up SCL SDA Ext pull up SDI SDO Ext pull up Ext pull up Ext pull up Ext pull up SINT N/C Ext pull up SPI IO I I I IO I I IO IO I IO IO IO I I I O O I IO/Z IO/Z O Pin Description Clock/SPI clock Chip Enable/NAND Chip Select/SPI Slave Select Address Bus 0/PNAND Command Latch Address Bus 1/PNAND Ready_Buy Addr. Bus [3:2] Addr. Bus 4/NAND Write Protect Address Bus 5/I2C clock Address Bus 6/I2C data Addr. Bus 7 SPI Input/Data Bus 0 SPI Output/Data Bus 1 Data Bus Address Valid Output Enable Write Enable Interrupt Request DMA Request DMA Acknowledgement USB D+ USB DExternal USB Switch Control UVDDQ UVSSQ PVDDQ VGND Power Domain P-PORT U-Port A6 A7] DQ[0] DQ[1] DQ[15:2] ADV# OE# WE# INT# DRQ# DACK# D+ DUVALID Document #: 001-11710 Rev. *A Page 3 of 6 [+] Feedback ADVANCE INFORMATION CYWB0224ABS/CYWB0224ABM Table 1. Astoria Pin Assignments (continued) Pin Name Non-multiplexing SDIO and NAND Configuration SD_D[7:0] SD_CLK Multiplexing NAND only Configuration SRAM Dual SDIO Configuration PNAND NAND and GPIO Configuration NAND_IO[15:8] / PD[7:0] (GPIO) PC-7 (GPIO) / NAND_CE8# / NAND_R/B4# PC-3 (GPIO) / NAND_CE7# / NAND_R/B3# PC-6 (GPIO) / NAND_CE6# PC-1 (GPIO) / NAND_CE5# NAND_IO[7:0] NAND_CLE NAND_ALE NAND_CE# NAND_RE# NAND_WE# NAND_WP# NAND_R/B# SD2_WP RESETOUT PC-4 (GPIO[0]) / SD_CD PC-5 (GPIO[1]) / SD2_CD NAND_CE2# NAND_R/B2# / RESETOUT PC-4 (GPIO[0]) / NAND_CE4# PC-5 (GPIO[1]) / NAND_CE3# PC-2 (GPIO) RESETOUT PC-4 (GPIO[0]) / SD_CD PC-5 (GPIO[1]) SPI SDIO and GPIO Configuration SD_D[7:0] SD_CLK IO IO SD Data bus/NAND Upper IO bus SD Clock/NAND CE8#/NAND R/B4# IO Pin Description Power Domain NAND_IO[15:8] SD_D[7:0] / PD[7:0] (GPIO) NAND_CE8#/N SD_CLK AND_R/B4# NAND_CE7#/N SD_CMD AND_R/B3# NAND_CE6# NAND_CE5# NAND_IO[7:0] NAND_CLE NAND_ALE NAND_CE# NAND_RE# NAND_WE# NAND_WP# NAND_R/B# NAND_CE2# NAND_R/B2# SD_POW SD_WP SD2_D[7:0] SD2_CLK SD2_CMD SD2_POW N/C N/C PA-5 (GPIO) SD_CMD SD_CMD IO SD Command, NAND CE7#, or NAND_R/B3# SD Power Control/NAND CE6# GPIO (SD Write Protection Microswitch) or NAND CE5# NAND Lower IO bus/2nd SD Data Bus CMD Latch Enable/2nd SD Clock Address Latch Enable/2nd SD CMD Chip Enable/2nd SD Power Control Read Enable Write Enable Write Protect Ready/Busy/2nd SD WP Chip Enable 2 RESET OUT/NAND Busy/Ready General Input/Output 0 or SD/MMC Card Detection or NAND CE4# General Input/Output 1 or NAND CE3# RESET Wake Up Signal Crystal/Clock IN Crystal Out Clock Select 0 and 1 S Port Configuration Test Configuration SSVDDQ VGND SD_POW SD_POW SD_WP PB[7:0] (GPIO) PA-6 (GPIO) PA-7 (GPIO) PC-0 (GPIO) N/C N/C PA-5 (GPIO) IO IO IO IO IO IO O O IO I IO IO IO S-Port SD_WP NAND_IO[7:0] NAND_CLE NAND_ALE NAND_CE# NAND_RE# NAND_WE# NAND_WP# NAND_R/B# NAND_CE2# RESETOUT / NAND_R/B2# SNVDDQ VGND GPIO[0] / SD_CD / NAND_CE4# NAND_CE4# Other GPIO[1] / NAND_CE3# RESET# WAKEUP XTALIN XTALOUT NAND_CE3# IO I I I O I I I GVDDQ VGND XVDDQ VGND GVDDQ VGND Config XTALSLC[1:0] NANDCFG TEST[2:0] PVDDQ SNVDDQ UVDDQ SSVDDQ GVDDQ PWR Processor interface VDD PWR NAND VDD PWR USB VDD PWR SDIO VDD PWR Miscellaneous IO VDD PWR Analog VDD PWR Crystal VDD PWR Core VDD PWR Independent 3.3V nominal PWR USB GND PWR Analog GND PWR Core GND Power AVDDQ XVDDQ VDD VDD33 UVSSQ AVSSQ VGND Document #: 001-11710 Rev. *A Page 4 of 6 [+] Feedback ADVANCE INFORMATION CYWB0224ABS/CYWB0224ABM Ordering Information Ordering Code CYWB0224ABS-BVXI CYWB0224ABM-BVXI Package Type 100 VFBGA - Pb-Free 100 VFBGA - Pb-Free NAND Flash Support Support SLC NAND Flash only Support SLC and MLC NAND Flash Available Clock Input Frequencies (MHz) 19.2, 24, 26, 48 19.2, 24, 26, 48 Package Diagram Figure 1. 100 VFBGA (6 x 6 x 1.0 MM) BZ100A 51-85209 *B Document #: 001-11710 Rev. *A Page 5 of 6 [+] Feedback ADVANCE INFORMATION CYWB0224ABS/CYWB0224ABM Document History Page Document Title: CYWB0224ABS/CYWB0224ABM West BridgeTM AstoriaTM Document Number: 001-11710 REV. ** *A ECN NO. 567055 Issue Date See ECN Orig. of Change VSO New data sheet Description of Change 1830226 See ECN VSO/AESA In the Feature list, adding the bullets of "N-Xpress Controller Technology" and "Multimedia Device Support" In the Feature list, removed the bullet of "Mass Storage device support" Update the bullet of Application Update Logic Block Diagram. Updated the section of "NAND Port" to N-Xpress NAND Controller" Updated the pin Assignment Table Fix the typo of VGAN in pin Assignment Table (c) Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-11710 Rev. *A Revised December 7, 2007 Page 6 of 6 West Bridge and Antioch are trademarks of Cypress Semiconductor Corporation. All other trademarks or registered trademarks referenced herein are the property of their respective owners. [+] Feedback |
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